1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including transistor elements comprising gate structures on the basis of a high-k gate dielectric material in combination with a metal electrode material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface defined by highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated there-from by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide based dielectrics as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the resulting work function and thus threshold voltage of the transistor structures. For instance, during a corresponding manufacturing sequence, the high-k material may be exposed to oxygen, which may result in an increase of layer thickness and thus a reduction of the capacitive coupling. Moreover, a shift of the work function may be observed when forming appropriate work function metals in an early manufacturing stage, which is believed to be caused by a moderately high oxygen affinity of the metal species, in particular during high temperature processes which may typically be required for completing the transistor structures, for instance for forming drain and source regions and the like.
For this reason, in some approaches, the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and the actual electrode metal and the final adjustment of the work function of the transistors may be accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure.
According to this approach, in particular, any threshold variations caused by high temperature processes and the like may be efficiently avoided, thereby contributing to superior uniformity of sophisticated transistor elements. In the replacement gate approach, the polysilicon material is removed on the basis of appropriate etch recipes, such as wet chemical etch processes, which exhibit a high degree of selectivity with respect to the insulating material that laterally delineate the polysilicon material. After the removal of the polysilicon material, an appropriate metal-containing material is deposited in order to form the work function adjusting species above the gate dielectric material as explained above. Typically, P-channel transistors and N-channel transistors require different types of work function adjusting species, which may require a corresponding masking and patterning regime in order to appropriately form the desired work function adjusting material in the gate electrode structures of P-channel transistors and N-channel transistors, respectively. Irrespective of the applied process strategy after depositing the work function adjusting material layer, at least the actual electrode metal, such as aluminum, has to be filled into the opening, the width of which may, however, be further reduced by the previous deposition of the work function adjusting material, thereby causing significant irregularities, as will be explained with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 that comprises a substrate 101, such as a silicon substrate and the like, in or above which is provided a silicon-based semiconductor layer 102. Furthermore, the device 100 comprises a transistor 150, such as a P-channel transistor or an N-channel transistor, that may be formed on the basis of critical dimensions of approximately 40 nm and less. Furthermore, a further circuit element 160, such as a field effect transistor, a capacitor and the like, is provided in the semiconductor device 100 and may be formed on the basis of a greater critical dimension. The transistor 150 comprises drain and source regions 151, possibly in combination with metal silicide regions 152. Similarly, the circuit element 160 comprises “drain and source” regions 161 in combination with metal silicide regions 162. Furthermore, the transistor 150 comprises a gate electrode structure 155 which, in the manufacturing stage shown, includes a gate dielectric material 155A formed on the basis of a high-k dielectric material, as discussed above. Furthermore, a sidewall spacer structure 155C is provided and defines an opening 155O having a width that substantially corresponds to a desired length of the gate electrode structure 155. For example, a width of the opening 155O may be 40 nm and less in sophisticated applications. Similarly, the circuit element 160 may comprise a “gate electrode structure” 165 including a gate dielectric material 165A, a spacer structure 165C, which defines an opening 165O. In principle, the gate electrode structures 155, 165 may have the same configuration except for a different width of the opening 165O compared to the opening 155O. Furthermore, a dielectric material 103, for instance in the form of silicon nitride, silicon dioxide and the like, is provided so as to laterally enclose the gate electrode structures 155, 165.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following process techniques. After forming appropriate semiconductor regions in the layer 102, for instance by providing isolation structures (not shown) for receiving the circuit elements 150, 160, the gate dielectric materials 155A, 165A may be formed on the basis of oxidation and/or sophisticated deposition techniques, wherein, typically, a high-k dielectric material is incorporated in the dielectric materials 155A, 165A. For instance, a silicon oxide-based material may frequently be used as a base layer, possibly in combination with other species, such as nitrogen, on which an appropriate high-k dielectric material, such as hafnium oxide and the like, may be deposited. Thereafter, a conductive cap material may be formed in order to enhance integrity of the gate dielectric materials 155A, 165A during the further processing. Thereafter, polysilicon material is deposited on the basis of well-established process recipes, possibly in combination with further cap materials, hard mask materials and the like, as is required for patterning the resulting material layer stack in accordance with the design rules so as to reliably implement the critical dimensions for the gate electrode structure 155. Thereafter, sophisticated patterning processes are applied in order to obtain the gate electrode structures 155, 165, which include the polysilicon material as a placeholder material. Next, the drain and source regions 151, 161 may be formed in combination with the sidewall spacer structures 155C, 165C in order to obtain the desired dopant profile. Further-more, the spacer structures 155C, 165C may also be used for forming the metal silicide regions 152, 162, thereby completing the basic configuration of the circuit elements 150, 160. Next, the dielectric material 103, also referred to as an interlayer dielectric material, is formed, for instance, by depositing silicon nitride followed by silicon dioxide and the like. Thereafter, any excess material may be removed and an upper surface of the gate electrode structures 155, 165 is exposed, for instance, by a polishing process, such as chemical mechanical polishing (CMP). Next, an etch process, such as a highly selective wet chemical etch process, is performed to remove the exposed polysilicon material selectively to the dielectric material 103 and the sidewall spacer structures 155C, 165C, thereby forming the openings 155O, 165O.
FIG. 1b schematically illustrates the semiconductor device 100 with a metal-containing material layer 155D formed on the dielectric material 103 and in the openings 1550, 1650. The material layer 155D comprises one or more layers of different materials, such as titanium nitride, tantalum nitride and the like, wherein an appropriate metal species, such as lanthanum, aluminum and the like, may also be incorporated in order to adjust the resulting work function of the gate electrode structures 155, 165. As previously discussed, depending on the overall process strategy, different material layers may locally be provided in transistors of different conductivity type, thereby requiring the deposition of at least one or more material layers, possibly in combination with additional etch processes for selectively removing one or more of these layers from gate electrode structures of transistors which may require a different type of work function metal species. Irrespective of the process strategy applied, the material 155D may be deposited on the basis of sophisticated deposition techniques, such as chemical vapor deposition, physical vapor deposition and the like, so as to form the material layer 155D reliably at least above the gate dielectric materials 155A, 165A with a thickness as required for appropriately positioning the work function metal species at and in the dielectric materials 155A, 165A. During the deposition of the material 155D, a significant variation of the layer thickness may be created, which may be particularly pronounced in an upper portion of the opening 155O of reduced critical dimension. Thus, while a width 155W of the opening 155O at the bottom thereof may be defined by the local layer thickness that is selected so as to obtain the desired coverage of the gate dielectric material 155A, a width 155R at the top of the opening 155O may be significantly reduced due to corresponding overhangs of the layer 155D. On the other hand, the reduced width 165R at the top area of the opening 165O may not substantially affect the further processing of the device 100. On the other hand, the reduced width 155R, which may be 20 nm and even less for an initial width of the opening 155O of approximately 40 nm, may result in significant irregularities during the further processing when filling in an actual electrode material into the openings 155O, 165O.
FIG. 1c schematically illustrates the semiconductor device 100 after the deposition of an electrode metal 155E, such as aluminum and the like, in order to complete the gate electrode structures 155, 165. Due to the reduced width 155R (FIG. 1b), the opening 155O may not be completely filled or the opening 155O may even remain substantially non-filled, thereby producing a non-functional gate electrode structure for the transistor 150. On the other hand, the opening 165O may be reliably filled due to the less critical width of the opening 165O. Consequently, upon removing any excess material, the gate electrode structures 155, 165 may be completed, however, with a very pronounced probability of creating non-functional gate electrode structures for critical transistor elements, such as the transistor 150. Thus, although, in principle, the adjustment of the work function of the gate electrode structure 155 in a very advanced manufacturing stage may be advantageous in view of reducing transistor variability in terms of threshold voltage variations, in particular, highly scaled transistor elements may suffer from an increased yield loss due to incompletely filled gate electrode structures or non-functional gate electrode structures.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.